Redundant storage latches or storage cells include multiple storage nodes to store multiple instances of a logic value. Redundant storage cells are used in soft error upset tolerant (SEUT) circuits.
Redundant storage cells include a plurality of dual logic level write circuits to write to a corresponding plurality of same sense storage nodes. Dual logic level gate structures include complex interconnections, consume valuable space, and add parasitic capacitances to other circuits.
Redundant storage cells include storage cells having feedback interlock circuitry to generate feedback loops to maintain stored logic values, and circuitry to disable the feedback loops during a subsequent write operation. The circuitry to disable the feedback loops consumes additional space.
In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.